The present invention relates generally to a buffer storage control technique for a computer system, and more particularly to a buffer storage control technique for allowing data transfer among the buffer storages of a multi-processor system which includes a plurality of the buffer storages.
In general, a computer system includes a high-speed instruction processor, a main storage of low-speed and large capacity and one or more buffer storages of high-speed and small capacity. The computer system can perform operations at high speed due to combined use of the high-speed instruction processor, and a two-level hierarchical arrangement of the storages inclusive of the main storage and the buffer storages. More specifically, in a computer system equipped with a buffer storage, the main storage data which is used at a high frequency is stored in the buffer storage so that the desired data can be obtained by consulting the buffer storage, with a view to reducing the effective main storage access time and thereby enhancing the processing capability of the processor. The main storage is constituted by a dynamic RAM (Random Access Memory) which is commonly implemented by metal oxide semiconductor (MOS) transistors. On the other hand, the buffer storage is constituted by a static RAM which is usually implemented by bipolar transistors.
Besides the two-level hierarchical storage arrangement, it is equally possible to implement a multi-level hierarchical memory structure by providing additional storage devices. As a storage method for a memory of hierarchical structure, there can generally be mentioned a store-through method according to which updating of data at a given level is immediately followed by the updating of data at lower levels and a store-in method according to which data of a low level is updated at the time when the updated data of higher level is returned to the low level.
Although the present invention is applicable to both store-through and store-in type systems, the following description will be made on the assumption that the invention is applied to a store-in type computer system.
In a store-in type computer system, it is noted that, when a relevant block exists in buffer storage upon occurrence of a store request, data in that block in the buffer storage is rewritten and returned to the main storage when that block is to be replaced.
Heretofore, in a multi-processor system including a plurality of buffer storages implemented in the store-in scheme, addresses of blocks, each representing a unit for handling a series of data in the buffer storage, are transmitted for effecting data transfer among the buffer storages for the purpose of realizing a coincidence in the control of the buffer storages. More specifically, when desired data is absent from a given one of the buffer storages, the relevant block address is sent out to another buffer storage, whereon a decision is made as to whether or not the relevant block exists in the other buffer storage. In case the relevant block exists in the other buffer storage, and when the content thereof is different from that of the main storage because of having been rewritten, data of that block is transferred to the buffer storage in which the data request originates, to be stored therein. This type of buffer storage control system is disclosed, for example, in JP-A-61-290550.
In the case of the prior art buffer storage control system, no consideration is given to the sequence in which the data within the block is transferred at the time of data transfer between the buffer storages on a block basis, and so the transfer typically is carried out starting from the leading data. Accordingly, when the data required by a processor exists at a rear or trailing area in the block, there results a delay in the transmission of the required data to the processor from the buffer storage to which the data request is issued, giving rise to a problem.